1. Field of the Invention
The present invention relates to voltage-controlled oscillators and more specifically to the voltage-controlled oscillators typically found in phase-locked loop circuits.
2. Art Background
The functional blocks of a typical frequency multiplying phase-locked loop ("PLL") are shown in FIG. 1. Phase frequency detector 10 is a circuit that compares the frequency of reference input 11 with that of feedback input 12. The feedback frequency is the frequency of voltage controlled oscillator 13 divided by the feedback divide-by-n 14. Filter 15 converts digital phase information from phase frequency detector 10 to the analog control 16 necessary for the oscillator 13.
The frequency range of the oscillator 13 must be large enough to ensure that filter 15 can force the correct frequency from within the range of its control output 16. If the oscillator 13 were to run at too high a frequency, it may be possible that the control 16 would be unable to force it to the proper frequency. In that case the logic will run at an incorrect frequency and produce unexpected effects. It is also possible that the oscillator 13 could run faster than the feedback logic could follow. If that were to happen, feedback 12 to phase frequency detector 10 would appear slower than expected and would cause an incorrect adjustment, and the oscillator 13 would be forced to even higher frequencies.
FIG. 2 is a representation of a typical voltage-controlled oscillator 20 that can be used for clock generation in PLL circuits shown in FIG. 1. It is constructed of consecutive stages of gates and multiplexers. This oscillator 20 offers the convenience that it is made from logic gates identical to those used in the other logic in the chip and will react in the same way to environmental changes and to process variations. Voltage-controlled oscillator 20 ("VCO") consists of a ring oscillator that can have its effective length changed in response to a control input. As control input 21 (Vcon) is skewed from its logic "LOW" to its logic "HIGH," the oscillator 20 changes smoothly from its lowest frequency to its highest frequency. This change in frequency is achieved by the analog nature of the multiplexers 22-27 used, and their ability to "ADD" the effective delays at the two inputs as Vcon 21 is swept between the LOW and HIGH logic levels. It behaves nicely as its control limits are reached, since each limit only selects either a minimum-gate-delay or maximum-gate-delay defined frequency. Different frequency limits can be achieved by changing the number of multiplexer ("MUX")/delay stages, and/or the number of delay stages per stage .
The schematic diagrams of typical PLL elements shown in FIGS. 3(a) and 3(b) are illustrated in FIGS. 3(c) and 3(d) respectively. FIGS. 3(a) and 3(c) illustrate a typical CML ("Current-Mode Logic") differential pair with Vcs as its voltage current source. FIGS. 3(b) and 3(d) illustrate a typical CML MUX using two differential pairs with a common Vcs. Complimentary input signals are applied to the bases of the differential pair 31 and 32. Complimentary select signals are applied to the common-emitter pair 33 with Vcs as its voltage current source. These circuits are typical of those used in CML circuitry as will be appreciated by those skilled in the art.
The prior circuit has its disadvantages. Since the oscillator 20 as shown in FIG. 2 is made from almost any number of successive stages of identical gates and has a cumulative delay that is much longer than the delay through a single element, it is possible that it could oscillate in more than one mode. In normal operation, a single cycle of "one to zero to one" transitions will circulate. If the gates are disturbed, or if they assume certain initial conditions as the oscillator is powered on, it is possible to get multiple cycles circulating within the ring (more than one inversion within the ring). This will cause the oscillator to appear to be running at some multiple, possibly not symmetrical, frequency with no way to recover. If this happens, the product in which this oscillator resides will appear to have failed. For short rings with 2-4 stages, it is unlikely that any alias would be possible, since the total period of oscillation is only slightly longer than the individual stage delays, and the analog adder (i.e. the MUX) would degenerate to a single mode. However, for longer rings, the MUX would find multiple transitions indistinguishable from the normal operation of the ring and would sustain them.
Furthermore, the circuit illustrated in FIG. 1 has other drawbacks. Because circuit 10 is used to create frequencies within an integrated circuit from an external reference frequency, this makes the test of the product more difficult because of the nature of the PLL circuits.
In a typical circuit containing a PLL, test modes are added to facilitate factory testing. One way to add these functions is to add a MUX that will allow the user to insert an external clock in place of the internal VCO clock so that automated test Equipment (ATE) can more efficiently test the product function. A typical connection is shown in FIG. 4. Note that test mode 41 selects the inputs to MUX 43, which receives inputs from external clock 42 and VCO output 44.
Although the traditional technique shown in FIG. 4 allows efficient test of the product's function, it leaves the PLL and all of its components untested. As a result, further testing is required to verify both function and parametric values for the PLL.
As will be described in the following, the present invention provides an apparatus for initializing the VCO of a PLL circuit to ensure that it runs at the intended frequency. Also, the present invention provides a method and apparatus for adding increased testability to circuits containing the PLL.